(1) Field of the Invention
The present invention relates to the technology of decode processing for address signals in SRAMs (Static RAM) provided for processor devices such as CPUs (Central Processing Units).
(2) Description of the Related Art
SRAM (Static RAM) circuits, which are used in registers of CPUs (Central Processing Units) and cache memories, are provided with multiple memory cells for storing data therein, which memory cells are arranged in an array form.
FIG. 7 is a view showing a decode circuit and a memory cell of an SRAM. FIG. 8 is a diagram showing the decode circuit of FIG. 7 as a combination of two parts thereof: a predecoder; and a main decoder. In this instance, in the examples of FIG. 7 and FIG. 8, only one of the multiple memory cells is illustrated. FIG. 9 is a view showing a decode circuit and memory cells of a previous SRAM. This example is realized by a NAND circuit which is formed by a dynamic circuit {a circuit in which precharging is performed by a single pMOS circuit [p channel MOS (Metal Oxide Semiconductor)] and a logic function is configured with multiple nMOS (n channel MOS) circuits, when no clock is input}.
Hereinafter, to configure a circuit using a dynamic circuit will sometimes be referred to as “to dynamize a circuit”.
As shown in FIG. 7, an SRAM 50 includes multiple memory cells 51 arranged in an array form (cell array 53; see FIG. 9) and a decode circuit (decoder) 52. These decode circuit 52 and memory cells 51 are connected to each other through a word line (select signal line) 54.
The decode circuit 52 decodes (address decoding) address signals, and is provided one for each memory cell 51. The decode circuit 52 decodes address signals received from outside the SRAM 50 and activates a word line 54 corresponding to the decode result, whereby read/write processing to the corresponding memory cell 51 is carried out.
Hereafter, reference character AD[*] (*is an integer of 0 through i−1; i is a natural number expressing the bit width of the address) denotes an input address, and the address signals corresponding to the input address are input. Further, reference character PC designates a precharge signal, and reference character EN designates an enable signal.
The example of FIG. 9 shows a construction of a decode circuit 52 which activates a memory cell 51-2, out of the memory cells 51-1 through 51-5 forming the cell array 53.
Generally speaking, as shown in FIG. 8 and FIG. 9, the decode circuit 52 is formed by two parts, a predecode circuit (predecoder) 521 and a main decode circuit (main decoder) 522, with consideration paid to the circuit size, wiring convenience, and delay. The predecoder 521 is equipped with decode units 55a formed by multiple combination logic circuits, and the main decoder 522 is equipped with decode units 55b also formed by multiple combination logic circuit. In FIG. 9, for convenience of illustration, only one decode unit 55b is shown.
In the predecoder 521, address signals are input to each of the decode units 55a and subjected to predecode processing. After that, the output signals from the decode units 55a are input to the decode units 55b of the main decoder 522 and subjected to main decode processing.
Further, as to the previous SRAM 50, these predecoder 521 and main decoder 522 are realized by NAND logics in the decode process in which the decode construction is divided into a predecoder and a main decoder, from the view point of good compatibility due to a construction using negative logic.
Enhanced speed in address decode processing is demanded in the art of SRAM 50. For example, the following patent document 1 discloses an art in which address signals are propagated to a decoder before a control signal which gives instructions about an operation of memory cells is activated. As a result, a decoder is activated after the activation of the control signal, thereby outputting decode signals, so that the speed of access is increased and erroneous operations are prevented.
The following techniques for increasing the speed of address decoding in an SRAM 50 are also used: dynamizing of a static circuit; increasing driving power, thereby improving delay; reducing the number of stages of n channel transistor tree connected in series and adjustment of the size thereof.
Here, as shown in FIG. 9, dynamizing of the static circuit is a technique in which a circuit is formed using only nMOS transistors, without using pMOS transistors. As a result, since the load of pMOS transistors can be reduced, the circuits are improved in speed.
[Patent Document 1] Japanese Patent Application Laid-open No. 2002-63792
However, in such previous SRAMs, if the drive power (drive ability) of transistors is simply increased for the purpose of increasing the speed of address decoding, the size of transistors is increased, so that the layout area is enlarged and the input capacity of a decoder and power consumption are increased.
Further, in cases where decode processing is realized by NAND logic, assuming that the number of address inputs is N, and that the number of predecoder inputs is i, the number of inputs to the main decoder is j=CELL (N/i) (CELL(x) . . . a ceiling function for x). Even though dynamizing is performed, the gate pass time in parallel with the (i+j) step (roughly estimated) is necessary for the address decode processing.
Here, in place of NAND logic, NOR logic can be used to realize decode processing. Further, this NOR logic can be dynamized (dynamic NOR circuit). By realizing the decode circuit 52 using a dynamic NOR circuit, the decode time is made to be fixed (for example, two steps) regardless of the number of addresses, so that address decoding can be improved in speed.
However, when a decode circuit is realized by a dynamic NOR circuit, (1) its output maintains the state of “H” when it matches an input address, and (2) its output is changed from the state of “H” to “L” when it does not match an input address. That is, except for the time during which decoding is being performed, all the word lines 54 are activated, thereby increasing power consumption, so that it is not preferable from the standpoint of an operation.
FIG. 10 is a view showing a decode circuit and memory cells of a previous SRAM. In this example, the decode circuit 52 is realized by a dynamic NOR circuit, and an AND circuit is provided for an output of the main decoder 522. In the example of FIG. 10, also, only one decode unit 55b is illustrated for the convenience of illustration.
For the purpose of decreasing power consumption, the example of FIG. 10 is provided with an AND circuit 56 at the output end of the decode units 55b of the main decoder 522. To this AND circuit 56, an output of the main decoder 22 and an enable clock (EN_B) are input, and an output of the main decoder 22 is pulsed with this enable clock.
However, as shown in FIG. 10, since the previous SRAM 50 has an AND circuit 56 arranged at the output end of the main decoder 522, a circuit for generating an enable clock needs to be provided. In addition, in the main decoder 522, timing adjustment required to be performed among the outputs of the decode units 55b makes the circuit construction complicated, and timing adjustment is troublesome.
Further, an operation must be guaranteed against manufacturing variations caused by miniaturization and high-density packaging of semiconductor devices at the time of manufacturing of SRAMs 50. Hence, a sufficient set-up time (the minimum margin time from when a signal is defined to when a clock is changed) needs to be ensured.